Designers of integrated circuit devices (“chips”), generally application-specific integrated circuits (“ASIC”) or system-on-a-chip (“SOC”) type designs, may use prototyping as part of the electronic design automation process prior to manufacture of the chip by a foundry. Prototyping is one type of hardware-based functional verification that allows the circuit designer to observe the behavior of the circuit design under conditions approximating its final, manufactured performance. During prototyping, a circuit design, generally written with a hardware description language (“HDL”), which is often register transfer language (“RTL”) code, is programmed into one or more programmable logic chips, frequently field-programmable gate arrays (“FPGA”) on a prototyping board. FPGA-based prototypes are a fully functional representation of the circuit design, its circuit board, and its input/output (“I/O”) devices. FPGA prototypes generally run at speeds much closer to the clock speed at which the manufactured ASIC or SOC will run than other types of functional verification, thereby making such prototyping systems faster, which allows for more in depth verification. The circuit design prototype may also be inserted into another electronic circuit so that the circuit design prototype may be observed and tested in an environment in which the manufactured chip will be used. As such, circuit designers may use FPGA prototyping as a vehicle for software co-development and validation, increasing the speed and accuracy of system developments.
Exemplary hardware used in prototyping comprises FPGAs or other types of programmable logic chips, input/output circuitry, and interconnect circuitry connecting the programmable logic chips to each other and to the input-output circuitry. An example of commercial prototyping hardware includes the DN7006K10PCIe-8T manufactured by the DINI Group of La Jolla, Calif. The DN7006K10PCIe-8T features six Altera Stratix 3 3SL340 (FF1760) FPGAs, a configuration FPGA, global clock generation hardware, interconnect connecting the FPGAs to each other, input/output devices including an eight lane PCI Express Endpoint, and DDR SODIMM slots for the insertion of RAM.
ASIC and SOC chip designs typically have a large number of different user clocks, as many as several dozen user clocks resulting in hundreds of internal clock nets, because circuit designers find the use of multiple clocks to bestow certain performance advantages in their circuit designs. In order for prototyping to be most effective, the prototype needs to match as closely as possible the functionality of the circuit design as it will be manufactured, which includes the prototype using the same number of clocks as the circuit design. In most FPGA-based prototyping systems, clock signals are generated by a central clock generator that is on the prototyping board, but not part of any FPGA hosting a circuit design partition. These user clock signals are then distributed to each FPGA. Using this method of clock generation, there may be many user clock lines occupying a greater number of FPGA I/O pins than is desirable. However, unlike the manufactured chip, the FPGAs used for prototyping have a limited number of global resources to route clock signals. For example, a typical FPGA may only have sixteen global clock routing resources. When using prototyping to verify such chip designs, mapping the clocks of the design (“user clocks”) to the FPGA can cause problems. Notably, if a user clock is routed in the FPGAs using nets other than the global clock nets, for example because all the dedicated global clock routing resources are used by other user clocks, there may be significant delay, which results in hold time violations in the circuit receiving this user clock. Such violations are difficult to fix, and often cannot be solved simply by slowing down the overall operation of the prototyped design due to the very small data delay between logic.
Several other problems arise due to numerous user clocks in addition to simply running out of FPGA global clock resources. Many modern ASIC or SOC chip designs use some form of clock gating to save power, for example chips used in cellular telephones or other portable electronic devices. When certain portions of the chip are not in use, a clock gate may be disabled, preventing a clock from reaching that portion of the chip, reducing switching activity and saving power. However, when mapping the chip design to the FPGAs of the prototyping system, the FPGA software can treat the chip design as having more user clocks due to the clock gates and perceive that there are insufficient global clock resources available in the FPGA. For example, if a single user clock is separately gated to two different clock islands in the chip, the FPGA software may perceive three different nets, and therefore three different clocks: one clock incoming to the clock gate, a second clock for the first island, and a third clock for the second island. If only two global clock resources were available, the FPGA software may route the two clocks, but ignore the third, even though there is really only a single clock.
Another problem is that using a large number of user clocks greatly increases the place and route times for the FPGA. The amount of time needed for the FPGA software to perform timing analysis during place and route of the chip design in the FPGA increases exponentially with the number of user clocks.
Furthermore, if the flip-flops of the FPGA feature an enable pin, as is common in modern FPGA prototyping boards, complex gating logic may not always be converted automatically to work in this clock plus enable configuration. In additional, some clock distribution networks use multiplexers receiving multiple user clocks, for example so that a particular circuit can selectively receive a first clock at one time or a different user clock at another time. It may not possible to convert these multiplexers to a clock plus enable configuration in the FPGA circuit.